Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench

DOI10.1016/j.ipl.2003.12.007zbMath1183.68387OpenAlexW2093834030MaRDI QIDQ1029101

Mark B. Josephs, Hemangee K. Kapoor

Publication date: 9 July 2009

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.ipl.2003.12.007

zbMATH Keywords

formal verificationspecification languagesformal methodsasynchronous logic

Mathematics Subject Classification ID

Abstract data types; algebraic specification (68Q65)

Related Items

On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP

Uses Software

• Concurrency Workbench

Cites Work

• Receptive process theory
• Trace theory and VLSI design
• Handshake Circuits
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