A high level power model for network-on-chip (NoC) router

DOI10.1016/J.COMPELECENG.2008.11.023zbMath1191.68045OpenAlexW2050008353MaRDI QIDQ1040941

Nader Bagherzadeh, Seung Eun Lee

Publication date: 27 November 2009

Published in: Computers and Electrical Engineering (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.compeleceng.2008.11.023

zbMATH Keywords

interconnection networknetwork-on-chipmulti-processor system-on-chippower model

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10)

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