Full simulation coverage for SystemC transaction-level models of systems-on-a-chip

DOI10.1007/s10703-009-0075-zzbMath1186.68127OpenAlexW1981471464MaRDI QIDQ1041294

L. Maillet-Contoz, C. E. Helmstetter, Florence Maraninchi

Publication date: 2 December 2009

Published in: Formal Methods in System Design (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10703-009-0075-z

zbMATH Keywords

schedulingsimulationruntime verificationsystem-on-a-chiptest coveragedynamic partial order reductionloose timingtranslational modeling

Mathematics Subject Classification ID

Theory of software (68N99)

Related Items (1)

Full simulation coverage for SystemC transaction-level models of systems-on-a-chip

Uses Software

• VINAS-P
• veriSoft
• DART
• SystemC
• Pinapa
• Octagon

Cites Work

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• Full simulation coverage for SystemC transaction-level models of systems-on-a-chip
• Defining conditional independence using collapses
• Partial-order methods for the verification of concurrent systems. An approach to the state-explosion problem
• Recoverability of Communication Protocols--Implications of a Theoretical Study
• Time, clocks, and the ordering of events in a distributed system
• Dynamic partial-order reduction for model checking software
• Static Analysis

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