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Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder - MaRDI portal

Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder

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Publication:1045526

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DOI10.1631/jzus.A0820112zbMath1176.94009MaRDI QIDQ1045526

Wan-Yi Li, Lu Yu

Publication date: 15 December 2009

Published in: Journal of Zhejiang University. Science A (Search for Journal in Brave)

zbMATH Keywords

interpolation VLSI architecture AVS HDTV

Mathematics Subject Classification ID

Image processing (compression, reconstruction, etc.) in information and communication theory (94A08) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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