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Method of binary log-antilog evaluation in hardware for fast arithmetic- logical units. I - MaRDI portal

Method of binary log-antilog evaluation in hardware for fast arithmetic- logical units. I

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Publication:1069666

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zbMath0584.65006MaRDI QIDQ1069666

O. G. Smorodinova, V. G. Chachanidze, G. G. Asatiani

Publication date: 1985

Published in: Automation and Remote Control (Search for Journal in Brave)

zbMATH Keywords

error estimates logarithmic function fast arithmetic-logical units

Mathematics Subject Classification ID

Computation of special functions and constants, construction of tables (65D20) Exponential and trigonometric functions (33B10)

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