Hierarchical verification of asynchronous circuits using temporal logic

DOI10.1016/0304-3975(85)90223-3zbMath0584.94022OpenAlexW2080641824MaRDI QIDQ1070998

Edmund M. Clarke, Bud Mishra

Publication date: 1985

Published in: Theoretical Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0304-3975(85)90223-3

zbMATH Keywords

efficient algorithmCTLautomatic verification systemComputation Tree Logichierarchical verificationKripke Structurepropositional temporal logic of branching timeself-timed FIFO queue element

Mathematics Subject Classification ID

Other nonclassical logic (03B60)

Related Items (9)

Verification of a class of self-timed computational networks ⋮ Unified temporal logic ⋮ Characterizing finite Kripke structures in propositional temporal logic ⋮ Rewriting semantics of production rule sets ⋮ The Birth of Model Checking ⋮ From Philosophical to Industrial Logics ⋮ Automatic and hierarchical verification for concurrent systems ⋮ From Monadic Logic to PSL ⋮ The complexity of propositional linear temporal logics in simple cases

Cites Work

• A calculus of communicating systems
• Automatic verification of finite-state concurrent systems using temporal logic specifications
• Hardware Specification with Temporal Logic: An Example
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