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State machines and assertions: An integrated approach to modeling and verification of distributed systems

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Publication:1077153
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DOI10.1016/0167-6423(86)90002-XzbMath0594.68017OpenAlexW2056484775MaRDI QIDQ1077153

Thomas Räuchle, Thomas A. Joseph, Sam Toueg

Publication date: 1986

Published in: Science of Computer Programming (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0167-6423(86)90002-x

zbMATH Keywords

partial correctnessdeadlockalternating bit protocolassertional proofsaxiomatic verificationboundedness of channel sizefinite state analysisprotocols for asynchronous message passing systemsunspecified message receptionswindow flow control protocol


Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Theory of operating systems (68N25)


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Exposure to deadlock for communicating processes is hard to detect



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