An easily testable optimal-time VLSI-multiplier

DOI10.1007/BF00292108zbMath0602.94019MaRDI QIDQ1082330

Bernd Becker

Publication date: 1987

Published in: Acta Informatica (Search for Journal in Brave)

zbMATH Keywords

single stuck-at faultscellular fault modeltree-multiplierVLSI-design

Mathematics Subject Classification ID

Graph theory (including graph drawing) in computer science (68R10) Applications of graph theory to circuits and networks (94C15)

Related Items (1)

Computations over finite monoids and their test complexity

Cites Work

• Unnamed Item
• A logic-topological calculus for the construction of integrated circuits. I
• Detection of Faults in Programmable Logic Arrays
• Design of Testable Structures Defined by Simple Loops
• A Regular Layout for Parallel Adders
• The complexity of theorem-proving procedures
• Majority Gate Networks

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