A unified theory of interconnection network structure

DOI10.1016/0304-3975(86)90084-8zbMath0612.68032OpenAlexW1973383391MaRDI QIDQ1088405

Marc Snir, Clyde P. Kruskal

Publication date: 1986

Published in: Theoretical Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0304-3975(86)90084-8

zbMATH Keywords

routingBanyan networkdelta propertyfunctional propertiesbaseline networksbidelta networksdelta networksflip networksGraph-theoretical characterizationsindirect binary cube networkslabelling schemesmodified data manipulatorsmultistage networkomega networkspacket-switching networkprocessor networkstopology of interconnection networks

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Applications of graph theory to circuits and networks (94C15) Theory of operating systems (68N25) Theory of software (68N99)

Related Items (13)

Methods for message routing in parallel machines ⋮ Independent connections: An easy characterization of baseline-equivalent multistage interconnection networks ⋮ A graph theoretical approach to equivalence of multistage interconnection networks ⋮ Twin vertices in fault-tolerant metric sets and fault-tolerant metric dimension of multistage interconnection networks ⋮ A lower bound for sorting networks based on the shuffle permutation ⋮ MLMIN: a multicore processor and parallel computer network topology for multicast ⋮ The impact of randomization in smoothing networks ⋮ Cost-performance tradeoffs for interconnection networks ⋮ A theory of decomposition into prime factors of layered interconnection networks ⋮ All-to-all personalized exchange in generalized shuffle-exchange networks ⋮ Unnamed Item ⋮ Highly symmetric expanders ⋮ EFFICIENT ROUTING ALGORITHMS FOR GENERALIZED SHUFFLE-EXCHANGE NETWORKS

Cites Work

• Unnamed Item
• Notes on Shuffle/Exchange-Type Switching Networks
• On a Class of Multistage Interconnection Networks
• Access and Alignment of Data in an Array Processor
• The Indirect Binary n-Cube Microprocessor Array
• Data Manipulating Functions in Parallel Processors and Their Implementations

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