A logic-topological calculus for the construction of integrated circuits. II.

zbMath0633.94025MaRDI QIDQ1096590

Bernd Becker, Günter Hotz, Reiner Kolla, Paul Molitor

Publication date: 1986

Published in: Informatik. Forschung und Entwicklung (Search for Journal in Brave)

zbMATH Keywords

minimizationplanar graphprobabilistic algorithmlayerslayout problemannealing simulationbalanced layoutlayout of circuitslayout optimization problemstopology and topography of circuits

Mathematics Subject Classification ID

Applications of design theory to circuits and networks (94C30) Applications of graph theory to circuits and networks (94C15) Randomized algorithms (68W20)

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