Embedding ternary trees in VLSI arrays

DOI10.1016/0020-0190(87)90004-4zbMath0637.94025OpenAlexW2078660585MaRDI QIDQ1099135

Shlomit S. Pinter, Yaron Wolfstahl

Publication date: 1987

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0020-0190(87)90004-4

zbMATH Keywords

embedding complete ternary trees in VLSI arrays

Mathematics Subject Classification ID

Trees (05C05) Graph theory (including graph drawing) in computer science (68R10) Planar graphs; geometric and topological aspects of graph theory (05C10) Applications of graph theory to circuits and networks (94C15)

Related Items (1)

3 is more promising algorithmic parameter than 2

Cites Work

• The complexity of minimizing wire lengths in VLSI layouts
• Finding Two Disjoint Paths Between Two Pairs of Vertices in a Graph

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