Optimal three-dimensional layouts of complete binary trees

DOI10.1016/0020-0190(87)90045-7zbMath0637.94026OpenAlexW2024815945MaRDI QIDQ1099137

Ajay K. Gupta, Susanne E. Hambrusch

Publication date: 1987

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://docs.lib.purdue.edu/cgi/viewcontent.cgi?article=1523&context=cstech

zbMATH Keywords

volumeareabinary treeVLSIgraph layout

Mathematics Subject Classification ID

Trees (05C05) Graph theory (including graph drawing) in computer science (68R10) Planar graphs; geometric and topological aspects of graph theory (05C10) Applications of graph theory to circuits and networks (94C15)

Related Items (1)

Planar acyclic computation

Cites Work

• Unnamed Item
• Three-Dimensional VLSI
• Three-Dimensional Circuit Layouts
• Universality considerations in VLSI circuits
• Optimal three-dimensional VLSI layouts

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