The use of linear sums in exhaustive testing

DOI10.1016/0898-1221(87)90077-0zbMath0641.94034OpenAlexW2081035247MaRDI QIDQ1101069

S. B. Akers

Publication date: 1987

Published in: Computers \& Mathematics with Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0898-1221(87)90077-0

zbMATH Keywords

VLSIexhaustive testing

Mathematics Subject Classification ID

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Cites Work

• Exhaustive Test Pattern Generation with Constant Weight Vectors
• Verification Testing—A Pseudoexhaustive Test Technique
• Logic Test Pattern Generation Using Linear Codes
• Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
• The Weighted Syndrome Sums Approach to VLSI Testing

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