Functional test generation using binary decision diagrams

DOI10.1016/0898-1221(87)90072-1zbMath0641.94035OpenAlexW1980014718MaRDI QIDQ1101072

H. K. Reghbati, Magdy S. Abadir

Publication date: 1987

Published in: Computers \& Mathematics with Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0898-1221(87)90072-1

zbMATH Keywords

fault detectionintegrated circuitsbinary decision diagramsextension to the D-algorithmLSI/VLSI circuitnetwork of interconnected modules

Mathematics Subject Classification ID

Related Items

On the size of binary decision diagrams representing Boolean functions

Cites Work

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• Functional Level Primitives in Test Generation
• Test Generation for Microprocessors
• LSI logic testing — An overview
• A Module-Level Testing Approach for Combinational Networks
• Binary Decision Diagrams