Test schedules for VLSI circuits having built-in test hardware

DOI10.1016/0898-1221(87)90080-0zbMath0641.94036OpenAlexW2060598428MaRDI QIDQ1101073

Melvin A. Breuer, Magdy S. Abadir

Publication date: 1987

Published in: Computers \& Mathematics with Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0898-1221(87)90080-0

zbMATH Keywords

VLSIbuilt-in test techniquestest schedule

Mathematics Subject Classification ID

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Test schedules for VLSI circuits having built-in test hardware

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