Testing in two-dimensional iterative logic arrays

DOI10.1016/0898-1221(87)90074-5zbMath0641.94038OpenAlexW1973527898MaRDI QIDQ1101079

J. H. Patel, W.-T. Cheng

Publication date: 1987

Published in: Computers \& Mathematics with Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0898-1221(87)90074-5

zbMATH Keywords

combinational circuitcombinational cellsmultiple cell fault-modelsingle cell fault-modeltwo-dimensional iterative logic arrays

Mathematics Subject Classification ID

Related Items (1)

Computations over finite monoids and their test complexity

Cites Work

• Unnamed Item
• The Design of Easily Testable VLSI Array Multipliers
• A Testable Design of Iterative Logic Arrays
• Multiple Fault Detection in Arrays of Combinational Cells
• Truth-Table Verification of an Iterative Logic Array
• Testable Sequential Cellular Arrays

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