A systematic technique for detecting and locating bridging and stuck-at faults in I/O pins of LSI/VLSI chips

DOI10.1016/0898-1221(87)90076-9zbMath0641.94046OpenAlexW2080773155MaRDI QIDQ1101089

S. Y. H. Su, Shiyi Xu

Publication date: 1987

Published in: Computers \& Mathematics with Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0898-1221(87)90076-9

zbMATH Keywords

stuck-at faultsprinted circuit boardsbridging faultsarithmetic logic unitcompleteness of test setinput/output pins of integrated circuit chipsrandom access memoryVLSI chips

Mathematics Subject Classification ID

Cites Work

• Detecting I/O and Internal Feedback Bridging Faults
• Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets
• Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines
• Test Generation for Microprocessors
• Bridging and Stuck-At Faults

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