An algorithm to generate complete test sets for stuck-at faults in combinational logic circuits

DOI10.1016/0016-0032(88)90051-8zbMath0642.94047OpenAlexW2034924537MaRDI QIDQ1101421

David V. Kerns, Leonard J. Tung

Publication date: 1988

Published in: Journal of the Franklin Institute (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0016-0032(88)90051-8

zbMATH Keywords

algorithmstuck-at faultscombinational logic circuitscomponent connection modelfault simulation

Mathematics Subject Classification ID

Related Items (1)

An algorithm for stuck-at fault coverage analysis of combinational and sequential logic circuits

Cites Work

• Unnamed Item
• An Abstract Model for Digital System Fault Diagnosis
• An Algorithm for the Generation of Test Sets for Combinational Logic Networks
• A New Representation for Faults in Combinational Digital Circuits
• Multiple Fault Detection in Combinational Networks
• Fault Equivalence in Combinational Logic Networks

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