Verification of a class of self-timed computational networks

DOI10.1007/BF01937273zbMath0643.68019MaRDI QIDQ1102099

R. G. Melhem

Publication date: 1987

Published in: BIT (Search for Journal in Brave)

zbMATH Keywords

livenessformal verificationdeadlockalgebra of eventsself-timed computational networkssystolic networksVLSI cellular networks

Mathematics Subject Classification ID

Related Items (1)

The application of a sequence notation to the design of systolic computations

Cites Work

• Formal analysis of a systolic system for finite element stiffness matrices
• Hierarchical verification of asynchronous circuits using temporal logic
• An extensional treatment of dataflow deadlock
• Deadlock absence proofs for networks of communicating processes
• The application of a sequence notation to the design of systolic computations
• A Mathematical Model for the Verification of Systolic Networks
• A Theory of Communicating Sequential Processes
• Time, clocks, and the ordering of events in a distributed system

This page was built for publication: Verification of a class of self-timed computational networks