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VLSI systems for band matrix multiplication

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Publication:1104700
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DOI10.1016/0167-8191(87)90024-XzbMath0647.65029MaRDI QIDQ1104700

Kam Hoi Cheng, Sartaj K. Sahni

Publication date: 1987

Published in: Parallel Computing (Search for Journal in Brave)


zbMATH Keywords

effectivenessdesignsVLSI architecturesnumber of processorsband matrix multiplicationanalysis of performancesbus bandwidthdata movement stepserror diagnosissystolic systems


Mathematics Subject Classification ID

Theory of operating systems (68N25)


Related Items

Forty-three ways of systolic matrix multiplication ⋮ Designing of processor-time optimal systolic arrays for band matrix-vector multiplication



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