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Deadlock avoidance for systolic communication - MaRDI portal

Deadlock avoidance for systolic communication

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Publication:1104743

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DOI10.1016/0885-064X(88)90023-4zbMath0647.68029MaRDI QIDQ1104743

Publication date: 1988

Published in: Journal of Complexity (Search for Journal in Brave)

zbMATH Keywords

deadlock avoidance parallel processing system queue buffering systolic communication model

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Grammars and rewriting systems (68Q42) Theory of operating systems (68N25)

Related Items (1)

Deadlock-freeness of hexagonal systolic arrays

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