An optimistic ternary simulation of gate races

DOI10.1016/0304-3975(88)90107-7zbMath0651.94026OpenAlexW1969089599MaRDI QIDQ1106812

Carl-Johan H. Seger, Janusz A. Brzozowski

Publication date: 1988

Published in: Theoretical Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0304-3975(88)90107-7

zbMATH Keywords

binary almost- equal-delay modelbinary race analysisconsiderable importancecritical races and hazardsternary modeltiming problems in digital networks

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

Cites Work

• A Switch-Level Model and Simulator for MOS Digital Systems
• A Characterization of Ternary Simulation of Gate Networks
• On a Ternary Model of Gate Networks
• Hazard Detection in Combinational and Sequential Switching Circuits
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