VLSI architectures for string matching and pattern matching

DOI10.1016/0031-3203(87)90023-9zbMath0653.68096OpenAlexW2097493185MaRDI QIDQ1108057

S. H. Smith

Publication date: 1987

Published in: Pattern Recognition (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0031-3203(87)90023-9

zbMATH Keywords

VLSIstring matchingalgorithm partitiondynamic time-warp pattern matching

Mathematics Subject Classification ID

Pattern recognition, speech recognition (68T10)

Related Items (2)

VLSI architectures for string matching and pattern matching ⋮ APPLICATION-SPECIFIC ARRAY PROCESSORS FOR THE LONGEST COMMON SUBSEQUENCE PROBLEM OF THREE SEQUENCES ∗ †

Cites Work

• Algorithm partition and parallel recognition of general context-free languages using fixed-size VLSI architecture
• VLSI architectures for string matching and pattern matching
• Considerations in dynamic time warping algorithms for discrete word recognition
• Principles of animate vision
• Parallel Parsing Algorithms and VLSI Implementations for Syntactic Pattern Recognition
• A level building dynamic time warping algorithm for connected word recognition
• Dynamic programming algorithm optimization for spoken word recognition
• The String-to-String Correction Problem

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