Analysis and simulation of an out-of-order execution model in vector multiprocessor systems

DOI10.1016/S0167-8191(97)00095-1zbMath0903.68014MaRDI QIDQ1127444

M.-Tahar Kechadi, J.-Luc Dekeyser

Publication date: 13 August 1998

Published in: Parallel Computing (Search for Journal in Brave)

zbMATH Keywords

memory access conflictsout-of-order execution modelparallel memoriesvector multiprocessor systems

Mathematics Subject Classification ID

Computer system organization (68M99)

Related Items (1)

An exploration of instruction fetch requirement in out-of-order superscalar processors

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