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Testing and reconfiguration of VLSI linear arrays

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Publication:1128669
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DOI10.1016/S0304-3975(97)00238-7zbMath0902.68007MaRDI QIDQ1128669

Linda Pagli, Angelo Monti, Roberto De Prisco

Publication date: 13 August 1998

Published in: Theoretical Computer Science (Search for Journal in Brave)


zbMATH Keywords

fault detectionfault tolerancearray processorscatastrophic fault patternsreconfiguration algorithms


Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Computer system organization (68M99)


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An improved testing scheme for catastrophic fault patterns ⋮ Dynamic monopolies in tori. ⋮ Optimal irreversible dynamos in chordal rings ⋮ Local majorities, coalitions and monopolies in graphs: A review



Cites Work

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  • Counting the number of fault patterns in redundant VLSI arrays
  • Catastrophic faults in reconfigurable systolic linear arrays
  • Configuration of VLSI Arrays in the Presence of Defects
  • Efficient construction of catastrophic patterns for VLSI reconfigurable arrays
  • On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors
  • On reconfigurability of VLSI linear arrays
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