Area-time optimal VLSI networks for multiplying matrices

DOI10.1016/0020-0190(80)90006-XzbMath0445.94045OpenAlexW2057982630MaRDI QIDQ1145672

Jean E. Vuillemin, Franco P. Preparata

Publication date: 1980

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0020-0190(80)90006-x

zbMATH Keywords

matrix multiplicationarea-time complexityoptimal VLSI networks

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Numerical linear algebra (65F99)

Related Items

On the VLSI complexity of some arithmetic and numerical problems, Area-time tradeoffs for matrix multiplication and related problems in VLSI models, The matrix equation MX + XN = B in the VLSI model, An O(1) time optimal algorithm for multiplying matrices on reconfigurable mesh, Area-time tradeoff for rectangular matrix multiplication in VLSI models, Area-period tradeoffs for multiplication of rectangular matrices, New lower bound techniques for VLSI, The performance of multilective VLSI algorithms

Cites Work

• The Area-Time Complexity of Binary Multiplication