The complexity of a VLSI adder

DOI10.1016/0020-0190(80)90010-1zbMath0446.68037OpenAlexW2015518848MaRDI QIDQ1146001

Robert B. jun. Johnson

Publication date: 1980

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0020-0190(80)90010-1

zbMATH Keywords

area-time complexitybinary additionVLSI adder

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25)

Related Items (4)

Area-time lower-bound techniques with applications to sorting ⋮ On the VLSI complexity of some arithmetic and numerical problems ⋮ A VLSI fast solver for tridiagonal linear systems ⋮ Optimal tradeoffs for addition on systolic arrays

Cites Work

• The Area-Time Complexity of Binary Multiplication
• A Regular Layout for Parallel Adders

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