Delay-time modelling and critical-path verification for CMOS digital designs

DOI10.1016/0010-4485(91)90036-VzbMath0793.68183OpenAlexW1989047742MaRDI QIDQ1182347

S. Singh

Publication date: 28 June 1992

Published in: CAD. Computer-Aided Design (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0010-4485(91)90036-v

zbMATH Keywords

CADcomputer-aided designcritical pathdesign verificationCMOS delay timeCMOS digital circuitssemianalytic model

Mathematics Subject Classification ID

Computer science aspects of computer-aided design (68U07)

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