Fast algorithms for lowest common ancestors on a processor array with reconfigurable buses
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Publication:1183475
DOI10.1016/0020-0190(91)90082-SzbMath0742.68026OpenAlexW2023588769WikidataQ127498852 ScholiaQ127498852MaRDI QIDQ1183475
Publication date: 28 June 1992
Published in: Information Processing Letters (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/0020-0190(91)90082-s
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- Constant time sorting on a processor array with a reconfigurable bus system
- Two dimensional processor array with a reconfigurable bus system is at least as powerful as CRCW model
- Fast Algorithms for Finding Nearest Common Ancestors
- Finding Lowest Common Ancestors in Parallel
- Approximate Parallel Scheduling. Part I: The Basic Technique with Applications to Optimal Parallel List Ranking in Logarithmic Time
- On Finding Lowest Common Ancestors: Simplification and Parallelization
- Parallel Algorithms in Graph Theory: Planarity Testing
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