Parallelization of WHILE loops on pipelined architectures

DOI10.1007/BF00127840zbMath0742.68010MaRDI QIDQ1186817

Meng Lee, Michael S. Schlansker, Parthasarathy P. Tirumalai

Publication date: 28 June 1992

Published in: The Journal of Supercomputing (Search for Journal in Brave)

zbMATH Keywords

performance boundsdependence graphspipelined architecturesloop schedulingconditional executionModulo schedulingWHILE loops

Mathematics Subject Classification ID

Theory of compilers and interpreters (68N20) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Cites Work

• A composite hoisting-strength reduction transformation for global program optimization part I
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