Automatic verification of a class of systolic circuits

DOI10.1007/BF01212335zbMath0764.68093OpenAlexW2031444332MaRDI QIDQ1189257

Parosh Aziz Abdulla

Publication date: 26 September 1992

Published in: Formal Aspects of Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf01212335

zbMATH Keywords

automatic verificationsystolic circuitsdecision methods

Mathematics Subject Classification ID

Circuits, networks (94C99) Specification and verification (program logics, model checking, etc.) (68Q60) Reliability, testing and fault tolerance of networks and computer systems (68M15)

Cites Work

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• Reasoning about networks with many identical finite state processes
• Mechanical certification of systolic algorithms
• A Mathematical Model for the Verification of Systolic Networks
• Proving systolic systems correct
• Systolic arrays for Viterbi processing in communication systems with a time-dispersive channel
• Bounds on Positive Integral Solutions of Linear Diophantine Equations
• Hilbert's Tenth Problem is Unsolvable