Circuits over monoids: A fault model, and a trade-off between testability and circuit delay

DOI10.1016/0893-9659(92)90064-GzbMath0758.94019OpenAlexW1997899091MaRDI QIDQ1195687

Jean-Camille Birget, Hassan Farhat

Publication date: 5 January 1993

Published in: Applied Mathematics Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0893-9659(92)90064-g

zbMATH Keywords

transformation monoidfault modelevaluation circuitsprefix circuits

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Cites Work

• Parallel Prefix Computation
• Size-time complexity of Boolean networks for prefix computations

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