Analysis of hierarchical bus-based multicomputer architectures

DOI10.1016/0020-0190(92)90221-GzbMath0772.68010OpenAlexW2019283874WikidataQ126865139 ScholiaQ126865139MaRDI QIDQ1199955

A. S. Pombortsis

Publication date: 17 January 1993

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0020-0190(92)90221-g

zbMATH Keywords

hierarchical interconnection networksperformance modelsmulticomputer systems

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Computer system organization (68M99)

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