Performance analysis of clock-regulated queues with output multiplexing in three different 2x2 crossbar switch architectures

DOI10.1016/0743-7315(92)90041-KzbMath0763.68020OpenAlexW2016705403MaRDI QIDQ1200161

Susan R. Dickey, Ora E. Percus

Publication date: 17 January 1993

Published in: Journal of Parallel and Distributed Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0743-7315(92)90041-k

zbMATH Keywords

interconnection networksswitchesparallel shared memory computer

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

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