A methodology for algorithm regularization and mapping into time-optimal VLSI arrays

DOI10.1016/0167-8191(93)90104-SzbMath0794.68074MaRDI QIDQ1208500

S. Singh

Publication date: 16 May 1993

Published in: Parallel Computing (Search for Journal in Brave)

zbMATH Keywords

mappingsystolic architecturesystolic implementationalgorithmic transformationsgraph methodology for regularizing data flowsystolic directed graphsystolic precedence diagramtime-optimal VLSI arrays

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Mathematical problems of computer architecture (68M07)

Related Items (3)

The design of optimal planar systolic arrays for matrix multiplication ⋮ Designing of processor-time optimal systolic arrays for band matrix-vector multiplication ⋮ Matrix-vector multiplication on a fixed-size linear systolic array

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