A graph theoretical approach for the yield enhancement of reconfigurable VLSI/WSI arrays

DOI10.1016/S0166-218X(98)00091-2zbMath0913.68020OpenAlexW2004995420MaRDI QIDQ1276972

Chong S. Rim, Jagannathan Narasimhan, Kazuo Nakajima

Publication date: 2 February 1999

Published in: Discrete Applied Mathematics (Search for Journal in Brave)

Full work available at URL: http://www.elsevier.com/locate/dam

zbMATH Keywords

pebblescircuit placementcircuit reconfiguration problem

Mathematics Subject Classification ID

Computer system organization (68M99)

Cites Work

• Unnamed Item
• Unnamed Item
• Optimization by Simulated Annealing
• Planar 3DM is NP-complete

This page was built for publication: A graph theoretical approach for the yield enhancement of reconfigurable VLSI/WSI arrays