Analysis and identification of speed-independent circuits on an event model

DOI10.1007/BF01383956zbMath0786.94023MaRDI QIDQ1314511

V. Pereyra

Publication date: 17 February 1994

Published in: Formal Methods in System Design (Search for Journal in Brave)

zbMATH Keywords

verificationspecificationasynchronous circuitsdelay insensitivityevent specificationsignal graphspeed independence

Mathematics Subject Classification ID

Related Items (2)

ASYNCHRONOUS AUTOMATA NETWORKS CAN EMULATE ANY SYNCHRONOUS AUTOMATA NETWORK ⋮ Synthesising elementary net systems with localities

Cites Work

• Marked directed graphs
• Semi-modularity and testability of speed-independent circuits
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