A general performance analysis method for uniform memory architectures

DOI10.1007/BF01990534zbMath0797.68013OpenAlexW2085884129MaRDI QIDQ1317857

Ching-Roung Chou, Chiau-Shin Wang, Jong-Jeng Chen

Publication date: 22 March 1994

Published in: BIT (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf01990534

zbMATH Keywords

performance analysisMarkov chaininterconnection networksmultiprocessor systemcrossbargeneralized shuffle networkmemory bandwidthmultiple buses

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Cites Work

• Analysis of Memory Interference in Multiprocessors
• Access and Alignment of Data in an Array Processor

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