Expressibility of output equals input. Negative and positive results

DOI10.1007/BF01185565zbMath0790.68073OpenAlexW2051202886MaRDI QIDQ1323378

Telis Menas, Leo Marcus

Publication date: 10 May 1994

Published in: Acta Informatica (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf01185565

zbMATH Keywords

first-order logictemporal logicspecification language

Mathematics Subject Classification ID

Logic in computer science (03B70) Specification and verification (program logics, model checking, etc.) (68Q60)

Cites Work

• The analysis of concurrent systems. Cambridge, September 12-16, 1983. Proceedings
• Verifying concurrent processes using temporal logic
• An application of games to the completeness problem for formalized theories
• Can message buffers be axiomatized in linear temporal logic?
• Application of model theoretic games to discrete linear orders and finite automata
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