An exercise in the automatic verification of asynchronous designs

DOI10.1007/BF01384047zbMath0795.94020MaRDI QIDQ1329086

George A. McCaskill, George J. Milne, Andrew D. Bailey

Publication date: 4 September 1994

Published in: Formal Methods in System Design (Search for Journal in Brave)

zbMATH Keywords

automatic formal verification techniquecircal systemcircuit designs

Mathematics Subject Classification ID

Logic in artificial intelligence (68T27) Fault detection; testing in circuits and networks (94C12)

Related Items (2)

TTL: A modular language for hardware/software systems design. ⋮ On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP

Uses Software

• HOL

Cites Work

• CCS expressions, finite state processes, and three problems of equivalence
• Symbolic model checking: \(10^{20}\) states and beyond
• Testing equivalences for processes
• Generating BDDs for symbolic model checking in CCS
• CIRCAL and the representation of communication, concurrency, and time
• Graph-Based Algorithms for Boolean Function Manipulation
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