Counting the number of fault patterns in redundant VLSI arrays

DOI10.1016/0020-0190(94)00047-6zbMath0796.94022OpenAlexW2089845810MaRDI QIDQ1330668

Linda Pagli, Geppino Pucci

Publication date: 21 July 1994

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0020-0190(94)00047-6

zbMATH Keywords

distributed systemsperformance evaluationupper and lower boundsfault toleranceparallel processingVLSI circuitsnumber of minimal fault patterns

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Related Items (5)

Characterization of catastrophic faults in two-dimensional reconfigurable systolic arrays with unidirectional links ⋮ An improved testing scheme for catastrophic fault patterns ⋮ Catastrophic faults in reconfigurable systolic linear arrays ⋮ Testing and reconfiguration of VLSI linear arrays ⋮ On enumeration of catastrophic fault patterns

Cites Work

• Unnamed Item
• Configuration of VLSI Arrays in the Presence of Defects
• On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy

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