A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits

DOI10.1007/BF02085633zbMath0815.90129MaRDI QIDQ1339115

Alexandre A. Andreatta, Celso Carneiro Ribeiro

Publication date: 1 December 1994

Published in: Annals of Operations Research (Search for Journal in Brave)

zbMATH Keywords

tabu searchVLSI designgraph partitioningcircuit partitioninglogical testintegrated VLSI circuits

Mathematics Subject Classification ID

Programming involving graphs or networks (90C35) Applications of mathematical programming (90C90) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Parallel numerical computation (65Y05)

Related Items (1)

A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits

Uses Software

• Tabu search

Cites Work

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• Using tabu search techniques for graph coloring
• Partitioning circuits for improved testability
• New approaches for heuristic search: A bilateral linkage with artificial intelligence
• A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits
• The tabu search metaheuristic: How we used it
• Future paths for integer programming and links to artificial intelligence
• Graph partitioning applied to the logic testing of combinational circuits
• Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
• LSI logic testing — An overview
• The Weighted Syndrome Sums Approach to VLSI Testing
• `` Strong NP-Completeness Results

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