A Markov model for multibus multiprocessor systems under asynchronous operation

DOI10.1016/0020-0190(94)00230-VzbMath0875.68140OpenAlexW2080592909MaRDI QIDQ1349724

Hamed Nassar

Publication date: 27 February 1997

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0020-0190(94)00230-v

zbMATH Keywords

Performance evaluationInterconnection networksComputer architectureMultiprocessorsMultibus

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Computer system organization (68M99)

Cites Work

• Interleaved Memory Bandwidth in a Model of a Multiprocessor Computer System
• On a Class of Multistage Interconnection Networks
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