Scheduling divisible loads in bus networks with arbitrary processor release times
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Publication:1352761
DOI10.1016/0898-1221(96)00156-3zbMath0864.68004OpenAlexW2060614465MaRDI QIDQ1352761
Publication date: 19 February 1997
Published in: Computers \& Mathematics with Applications (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/0898-1221(96)00156-3
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