The design of optimal planar systolic arrays for matrix multiplication
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Publication:1356864
DOI10.1016/S0898-1221(97)00028-XzbMath0872.65040OpenAlexW1998203035MaRDI QIDQ1356864
I. Z. Milentijević, Emina I. Milovanović, Igor Ž. Milovanović, Mile K. Stojčev
Publication date: 19 October 1997
Published in: Computers \& Mathematics with Applications (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/s0898-1221(97)00028-x
Related Items (4)
A class of fault-tolerant systolic arrays for matrix multiplication ⋮ Forty-three ways of systolic matrix multiplication ⋮ Mapping matrix multiplication algorithm onto fault-tolerant systolic array ⋮ Matrix-vector multiplication on a fixed-size linear systolic array
Cites Work
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- Spacetime representations of computational structures
- Design and analysis of systolic algorithms and structures
- A methodology for algorithm regularization and mapping into time-optimal VLSI arrays
- The Design of Optimal Systolic Arrays
- Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
- Nonlinear transformations of the matrix multiplication algorithm
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