On the design of reliable Boolean circuits that contain partially unreliable gates
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Publication:1384528
DOI10.1006/jcss.1997.1531zbMath0897.68042OpenAlexW1984072326MaRDI QIDQ1384528
Yuan Ma, Leighton, Tom, Daniel J. Kleitman
Publication date: 4 August 1998
Published in: Journal of Computer and System Sciences (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1006/jcss.1997.1531
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Cites Work
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- Wafer-Scale Integration of Systolic Arrays
- Reliable computation by formulas in the presence of noise
- Invariance of complexity measures for networks with unreliable gates
- Fault Tolerant Sorting Networks
- Lower bounds for the complexity of reliable Boolean circuits with noisy gates
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