Processor array synthesis from shift-variant deep nested Do loops

DOI10.1023/A:1022028729196zbMath1039.68006OpenAlexW1502493174MaRDI QIDQ1402301

Yu Hen Hu, Surin Kittitornkun

Publication date: 20 August 2003

Published in: The Journal of Supercomputing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1022028729196

zbMATH Keywords

FPGAmotion estimationreconfigurable computingnested loopsystolic mapping

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

Uses Software

• Unnamed Item

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