Deviation-tolerant floating gate structures as a way to design an on-chip learning neural networks

DOI10.1007/S00500-001-0162-6zbMATH Open1039.68571OpenAlexW1964791325MaRDI QIDQ1403082

D. Massart

Publication date: 31 August 2003

Published in: Soft Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00500-001-0162-6

zbMATH Keywords

Artificial neural networks\(\nu\)MOS transistorAnalog hardware implementationDeviation tolerance

Mathematics Subject Classification ID

Learning and adaptive systems in artificial intelligence (68T05) Neural networks for/in biological studies, artificial life and related topics (92B20)

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