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Digit-serial complex-number multipliers on FPGAs - MaRDI portal

Digit-serial complex-number multipliers on FPGAs

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Publication:1405468

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DOI10.1023/A:1021197903170zbMath1039.68011OpenAlexW1787479024MaRDI QIDQ1405468

T. Sansaloni, Javier Valls, Keshab K. Parhi

Publication date: 25 August 2003

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1021197903170

zbMATH Keywords

FPGA Booth recoding complex-number multipliers digit-serial arithmetic

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

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