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An efficient IDCT processor design for HDTV applications - MaRDI portal

An efficient IDCT processor design for HDTV applications

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Publication:1405476

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DOI10.1023/A:1021154120916zbMath1039.68020OpenAlexW1571050259MaRDI QIDQ1405476

Jiun-In Guo, Jui-Cheng Yen

Publication date: 25 August 2003

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1021154120916

zbMATH Keywords

cyclic convolution HDTV adder-based implementation common sub-expression sharing inverse discrete cosine transform (IDCT)

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Computer system organization (68M99) Numerical algorithms for specific classes of architectures (65Y10)

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